UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 1163

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Current
Version
(U20024E)
1st edition
Edition
Addition of the 78K0R/KF3-L and 78K0R/KG3-L products.
Change of Documents Related to Devices and Documents Related to
Development Tools (Hardware) (User’s Manuals)
Addition of Caution 3 to 1.4.1 78K0R/KC3-L
Addition of Caution 3 to 1.4.2 78K0R/KD3-L
Addition of Caution 4 and Remark to 1.4.3 78K0R/KE3-L
Change of Table 2-3. Connection of Unused Pins
Change of description of the AMPH bit in Figure 7-3. Format of Clock Operation
Mode Control Register (CMC)
Addition of Note to Figure 7-4. Format of System Clock Control Register (CKC)
Change of Figure 7-15. Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte:
LVIOFF = 1))
Change of Caution 1 in Figure 7-16. Clock Generator Operation When Power
Supply Voltage Is Turned On (When LVI Default Start Function Enabled Is Set
(Option Byte: LVIOFF = 0))
Change of Table 7-4. CPU Clock Transition and SFR Register Setting Examples
(1/6) (2)
Change of Table 7-4. CPU Clock Transition and SFR Register Setting Examples
(2/6) (5)
Change of Table 7-8. Maximum Number of Clocks Required for f
Change of Table 7-9. Maximum Number of Clocks Required for f
Change of 8.3 (14) Noise filter enable registers 1, 2 (NFEN1, NFEN2)
Change of description of the AMPM bit in Figure 9-3. Format of Real-Time Counter
Control Register 0 (RTCC0)
Change of description of the RWAIT bit in Figure 9-4. Format of Real-Time
Counter Control Register 1 (RTCC1)
Change of description in 9.3 (8) Hour count register (HOUR)
Change of Figure 9-18. Procedure for Starting Operation of Real-Time Counter,
and addition of Note 2
Change of 9.4.5 1 Hz output of real-time counter
Change of 9.4.6 32.768 kHz output of real-time counter
Change of 9.4.7 512 Hz, 16.384 kHz output of real-time counter
Addition of Note 2 to Figure 10-4. Format of Comparator n Control Register
(CnCTL)
Change of Figure 10-8. Using the External Pin Input for the Comparator
Reference Voltage (Using Only a Comparator)
Change of Figure 10-9. Using the Internal Reference Voltage for the Comparator
Reference Voltage (Using Only a Comparator)
Change of Figure 10-10. Using the External Pin Input for the Comparator
Reference Voltage (Using a Comparator and a Programmable Gain Amplifier)
Change of Figure 10-11. Using the Internal Reference Voltage for the
Comparator Reference Voltage (Using a Comparator and a Programmable Gain
Amplifier)
Addition of Caution to Figure 10-12. Using the Programmable Gain Amplifier
Output Voltage as the A/D Converter Analog Input
Description
IH
MAIN
↔ f
APPENDIX B REVISION HISTORY
↔ f
MX
SUB
Throughout
Related Documents
CHAPTER 1 OUTLINE
CHAPTER 2 PIN
FUNCTIONS
(78K0R/KC3-L,
78K0R/KD3-L,
78K0R/KE3-L)
CHAPTER 7 CLOCK
GENERATOR
CHAPTER 8 TIMER
ARRAY UNIT
CHAPTER 9 REAL-TIME
COUNTER
CHAPTER 10
COMPARATORS/PROG
RAMMABLE GAIN
AMPLIFIERS
(78K0R/KC3-L,
78K0R/KD3-L,
78K0R/KE3-L only)
Chapter
(1/6)
1163