UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 1161

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Previous
version
(U19291E)
3rd edition
Edition
Change of Figure 12-81. Flowchart of UART Reception
Change of Note 2 in Table 12-3. Selection of Operation Clock
Addition of Note to 12.7.1 Address field transmission
Change of Figure 12-92. Timing Chart of Address Field Transmission
Addition of Note to 12.7.2 Data transmission
Change of Figure 12-95. Timing Chart of Data Transmission
Addition of Note to 12.7.3 Data reception
Change of Note 2 in Table 12-4. Selection of Operation Clock
Change of description of the STT bit in Figure 13-6. Format of IICA Control
Register 0 (IICCTL0) (3/4)
Change of Caution and description of the SPT bit in Figure 13-6. Format of IICA
Control Register 0 (IICCTL0) (4/4)
Change of Note in Figure 13-7. Format of IICA Status Register (IICS) (2/3)
Change of 13.4.2 Setting transfer clock by using IICWL and IICWH registers
Addition of Caution to 15.5.4 Holding DMA transfer pending by DWAITn bit
Addition of description to 15.5.5 Forced termination by software
Addition of Example 3 to Figure 15-11. Forced Termination of DMA Transfer (2/2)
Change of 15.6 (2) DMA response time
Change of 16.2 Interrupt Sources and Configuration
Change of Figure 18-5. STOP Mode Release by Interrupt Request Generation
(2/2)
Addition of (6) Internal reset by a reset processing check error
Change of Figure 19-1. Block Diagram of Reset Function
Change of Figure 19-3. Timing of Reset Due to Execution of Illegal Instruction
or Watchdog Timer Overflow
Change of Note 2 in Table 19-2. Hardware Statuses After Reset
Acknowledgment (3/4)
Change of Figure 19-5. Format of Reset Control Flag Register (RESF)
Change of Table 19-3. RESF Register Status When Reset Request Is Generated
Change of Figure 20-2. Timing of Generation of Internal Reset Signal by Power-
on-Clear Circuit and Low-Voltage Detector
Change of Figure 20-3. Example of Software Processing After Reset Release
(2/2)
Addition of Caution 4 to Figure 21-2. Format of Low-Voltage Detection Register
(LVIM)
Addition of Caution 4 to Figure 21-3. Format of Low-Voltage Detection Level
Select Register (LVIS)
Change of Figure 21-11. Example of Software Processing After Reset Release
(2/2)
Change of Caution 2 in Figure 22-1. Format of Regulator Mode Control Register
(RMC)
Change of Figure 23-1. Format of User Option Byte (000C0H/010C0H) (1/2)
Change of 23.4 Setting of Option Byte
Description
APPENDIX B REVISION HISTORY
CHAPTER 12 SERIAL
ARRAY UNIT
CHAPTER 13 SERIAL
INTERFACE IICA
CHAPTER 15 DMA
CONTROLLER
CHAPTER 16
INTERRUPT
FUNCTIONS
CHAPTER 18 STANDBY
FUNCTION
CHAPTER 19 RESET
FUNCTION
CHAPTER 20 POWER-
ON-CLEAR CIRCUIT
CHAPTER 21 LOW-
VOLTAGE DETECTOR
CHAPTER 22
REGULATOR
CHAPTER 23 OPTION
BYTE
Chapter
(6/7)
1161