UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 839

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The meanings of <8> to <19> in (3) Data ~ data ~ stop condition in Figure 15-33 are explained below.
Remark <1> to <19> in Figure 15-33 represent the entire procedure for communicating data using the I
<8> The master device sets a wait status (SCL0 = 0) at the falling edge of the 8th clock, and issues an interrupt
<9> The master device reads the received data and releases the wait status (WREL = 1).
<10> The ACK is detected by the slave device (ACKD = 1) at the rising edge of the 9th clock.
<11> The slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and the slave device issue
<12> The slave device writes the data to transmit to the IICA shift register (IICA) and releases the wait status that
<13> The master device issues an interrupt (INTIICA: end of transfer) at the falling edge of the 8th clock, and
<14> The master device sets NACK as the response (ACKE = 0) and changes the timing at which it sets the wait
<15> If the master device releases the wait status (WREL = 1), the slave device detects the NACK (ACK = 0) at
<16> The master device and slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and
<17> When the master device issues a stop condition (SPT = 1), the bus data line is cleared (SDA0 = 0) and the
<18> The slave device acknowledges the NACK, halts transmission, and releases the wait status (WREL = 1) to
<19> Once the master device recognizes that the bus clock line is set (SCL0 = 1) and after the stop condition
(INTIICA: end of transfer). The master device then sends an ACK by hardware to the slave device.
an interrupt (INTIICA: end of transfer).
it set by the slave device. The slave device then starts transferring data to the master device.
sets a wait status (SCL0 = 0). Because ACK control (ACKE = 1) is performed, the bus data line is at the
low level (SDA0 = 0) at this stage.
status to the 9th clock.
the rising edge of the 9th clock.
both the master device and slave device issue an interrupt (INTIICA: end of transfer).
master device releases the wait status. The master device then waits until the bus clock line is set (SCL0 =
1).
end communication. Once the slave device releases the wait status, the bus clock line is set (SCL0 = 1).
setup time has elapsed, the master device sets the bus data line (SDA0 = 1) and issues a stop condition.
The slave device detects the generated stop condition and both the master device and slave device issue
an interrupt (INTIICA: stop condition).
Figure 15-33 (1) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 15-33
(2) Address ~ data ~ data shows the processing from <3> to <12>, and Figure 15-33 (3) Data ~ data ~
stop condition shows the processing from <8> to <19>.
CHAPTER 15 SERIAL INTERFACE IICA
2
C bus.
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