UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 71

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
2.2.5 P40 to P43 (port 4)
clock output.
Remark √: Mounted
(1) Port mode
(2) Control mode
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
P40/TOOL0
P41/TOOL1
P42
P43
P40 to P43 function as an I/O port. These pins also function as data I/O for a flash memory programmer/debugger and
The following operation modes can be specified in 1-bit units.
(f) SDA10
(g) SCL10
(h) INTP1, INTP2
P40 to P43 function as an I/O port. P40 to P43 can be set to input or output port in 1-bit units using port mode
register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4).
Be sure to connect an external pull-up resistor to P40 when on-chip debugging is enabled (by using an option byte).
P40 to P43 function as data I/O for a flash memory programmer/debugger and clock output.
(a) TOOL0
This is a serial data I/O pin of serial interface for simplified I
This is a serial clock I/O pin of serial interface for simplified I
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
Caution To use P30/SO10/TxD1 and P32/SCK10/SCL10/INTP2 as general-purpose ports, set serial
This is a data I/O pin for a flash memory programmer/debugger.
Be sure to pull up this pin externally when on-chip debugging is enabled (pulling it down is prohibited).
communication operation setting register 02 (SCR02) to the default status (0087H). In addition,
clear port output mode register 3 (POM3) to 00H.
(
μ PD78F100y: y = 0 to 3)
40-pin
78K0R/KC3-L
√
√
−
−
CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
44-pin
(
μ PD78F100y: y = 1 to 3)
78K0R/KC3-L (48-pin)
√
√
−
−
2
C.
2
C.
(
μ PD78F100y: y = 4 to 6)
78K0R/KD3-L
√
√
−
−
(
μ PD78F100y: y = 7 to 9)
78K0R/KE3-L
√
√
√
√
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