UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 387

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
7.6.9 Conditions before clock oscillation is stopped
conditions before the clock oscillation is stopped.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remarks 1. The number of clocks listed in Table 7-7 to Table 7-9 is the number of CPU clocks before switchover.
Note The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
Note The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
Internal high-speed
oscillation clock
X1 clock
External main system clock
Subsystem clock
20 MHz internal high-speed
oscillation clock
Clock
2. Calculate the number of clocks in Table 7-7 to Table 7-9 by removing the decimal portion.
Set Value Before Switchover
Example When switching the main system clock from the internal high-speed oscillation clock to the
Table 7-10. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Note
(f
(f
CLK
CLK
Table 7-9. Maximum Number of Clocks Required for f
CSS
= f
0
1
= f
high-speed system clock (@ oscillation with f
MAIN
SUB
1 + f
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the internal high-speed
oscillation clock.)
MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the high-speed system clock.)
CLS = 0
(The CPU is operating on a clock other than the subsystem clock.)
SELDSC = 0
(The main system clock is operating on a clock other than the 20 MHz
internal high-speed oscillation clock.)
)
)
IH
/f
MX
= 1 + 8/10 = 1 + 0.8 = 1.8 → 2 clocks
Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled)
2 + f
(f
CLK
SUB
/f
= f
0
MAIN
MAIN
clock
Set Value After Switchover
)
IH
CSS
= 8 MHz, f
CHAPTER 7 CLOCK GENERATOR
1 + 2f
MAIN
MX
(f
CLK
MAIN
↔ f
= 10 MHz)
= f
1
/f
SUB
SUB
SUB
clock
Note
)
HIOSTOP = 1
MSTOP = 1
XTSTOP = 1
DSCON = 0
Flag Settings of SFR
Register
387