UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 1020

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Instruction
Stack
manipulate
Unconditio
nal branch
Conditional
branch
Group
2.
3.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
Mnemonic
PUSH
POP
MOVW
ADDW
SUBW
BR
BC
BNC
BZ
BNZ
BH
BNH
BT
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
When the program memory area is accessed.
This indicates the number of clocks “when condition is not met/when condition is met”.
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
register (CKC).
PSW
rp
PSW
rp
SP, #word
SP, AX
AX, SP
HL, SP
BC, SP
DE, SP
SP, #byte
SP, #byte
AX
$addr20
$!addr20
!addr16
!!addr20
$addr20
$addr20
$addr20
$addr20
$addr20
$addr20
saddr.bit, $addr20
sfr.bit, $addr20
A.bit, $addr20
PSW.bit, $addr20
[HL].bit, $addr20
ES:[HL].bit,
$addr20
Operands
Bytes
Table 29-5. Operation List (16/17)
2
1
2
1
4
2
2
3
3
3
2
2
2
2
3
3
4
2
2
2
2
3
3
4
4
3
4
3
4
Note 1 Note 2
2/4
2/4
2/4
2/4
2/4
2/4
3/5
3/5
3/5
3/5
3/5
4/6
1
1
3
1
1
1
1
1
1
1
1
1
3
3
3
3
3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Clocks
6/7
7/8
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
(SP − 1) ← PSW, (SP − 2) ← 00H,
SP ← SP − 2
(SP − 1) ← rp
SP ← SP − 2
PSW ← (SP + 1), SP ← SP + 2
rp
SP ← word
SP ← AX
AX ← SP
HL ← SP
BC ← SP
DE ← SP
SP ← SP + byte
SP ← SP − byte
PC ← CS, AX
PC ← PC + 2 + jdisp8
PC ← PC + 3 + jdisp16
PC ← 0000, addr16
PC ← addr20
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
PC ← PC+3+jdisp8 if (Z ∨ CY)=0
PC ← PC+3+jdisp8 if (Z ∨ CY)=1
PC ← PC + 4 + jdisp8 if (saddr).bit = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 4 + jdisp8 if PSW.bit = 1
PC ← PC + 3 + jdisp8 if (HL).bit = 1
PC ← PC + 4 + jdisp8
if (ES, HL).bit = 1
L
← (SP), rp
CPU
) selected by the system clock control
H
H
, (SP − 2)← rp
← (SP + 1), SP ← SP + 2
Operation
CHAPTER 29 INSTRUCTION SET
L
,
R
Z AC CY
Flag
R
R
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