UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 558

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, stop A/D conversion
Remark f
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
FR2
A/D Converter Mode Register (ADM)
0
0
0
0
1
1
1
1
×
×
0
0
0
0
1
1
1
1
FR1
0
0
1
1
0
0
1
1
×
×
0
0
1
1
0
0
1
1
2. The above conversion time does not include clock frequency errors. Select conversion time, taking
CLK
: CPU/peripheral hardware clock frequency
once (ADCS = 0) beforehand.
clock frequency errors into consideration.
FR0
0
1
0
1
0
1
0
1
×
×
0
1
0
1
0
1
0
1
LV1
0
0
1
1
LV0
0
1
0
1
Table 13-2. A/D Conversion Time Selection (2/3)
speed 1
speed 2
Normal
voltage
Mode
Low-
High
High
(2) 2.7 V ≤ AV
Setting prohibited
52.0
35.0
26.5
18.0
9.5
Setting prohibited
Setting prohibited
Setting prohibited
52.0
35.0
26.5
18.0
9.5
f
CLK
μ
μ
= 2 MHz
μ
μ
μ
μ
μ
μ
μ
μ
s
s
s
s
s
s
s
s
s
s
REF
Setting prohibited 34.2
34.4
27.6
20.8
14.0
10.6
Setting prohibited
Setting prohibited 34.2
34.4
27.6
20.8
14.0
10.6
7.2
3.8
f
Conversion Time Selection
CLK
μ
μ
≤ 5.5 V
= 5 MHz
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
s
s
s
s
s
s
s
s
s
s
s
s
17.2
13.8
10.4
Setting prohibited
17.2
13.8
10.4
7.0
5.3
3.6
Setting prohibited
f
CLK
μ
μ
μ
= 10 MHz
μ
μ
μ
μ
μ
μ
μ
μ
s
s
s
s
s
s
s
s
s
s
s
CHAPTER 13 A/D CONVERTER
17.1
8.6
Setting prohibited
17.1
8.6
6.9
5.2
3.5
Setting prohibited
f
CLK
μ
μ
μ
μ
μ
= 20 MHz
μ
s
μ
s
s
s
s
s
s
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
Conversion
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Clock (f
/20
/10
/8
/6
/4
/3
/2
/20
/10
/8
/6
/4
/3
/2
−
−
AD
)
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