UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 882

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(3) Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR10L, PR10H, PR11L, PR11H,
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
PR12L)
The priority specification flag registers are used to set the corresponding maskable interrupt priority level.
A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, or 2L).
The PR00L, PR00H, PR01L, PR01H, PR02L, PR10L, PR10H, PR11L, PR11H, and PR12L registers can be set by a
1-bit or 8-bit memory manipulation instruction. If the PR00L and PR00H, PR01L and PR01H, PR10L and PR10H,
and PR11L and PR11H registers are combined to form 16-bit registers PR00, PR01, PR10, and PR11, they can be
set by a 16-bit memory manipulation instruction. Using the PR02L register as the PR02 register and the PR12L
register as the PR12 register can be set also by using a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
Address: FFFE8H
Address: FFFECH
Address: FFFE9H
Address: FFFEDH
Symbol
Symbol
Symbol
Symbol
PR00H
PR10H
PR00L
PR10L
increases by 2 clocks.
(PR00L, PR00H, PR01L, PR01H, PR02L, PR10L, PR10H, PR11L, PR11H, PR12L) (1/2)
SREPR00
SREPR10
PPR05
PPR15
<7>
<7>
<7>
<7>
After reset: FFH
After reset: FFH
After reset: FFH
After reset: FFH
Figure 18-4. Format of Priority Specification Flag Registers
CSIPR001
CSIPR101
SRPR00
SRPR10
PPR04
PPR14
<6>
<6>
<6>
<6>
R/W
R/W
R/W
R/W
CSIPR000
CSIPR100
STPR00
STPR10
PPR03
PPR13
<5>
<5>
<5>
<5>
DMAPR01
DMAPR11
PPR02
PPR12
<4>
<4>
<4>
<4>
DMAPR00
DMAPR10
PPR01
PPR11
<3>
<3>
<3>
<3>
CHAPTER 18 INTERRUPT FUNCTIONS
CMPPR01
CMPPR11
PPR00
PPR10
<2>
<2>
<2>
<2>
CMPPR00
CMPPR10
LVIPR0
LVIPR1
<1>
<1>
<1>
<1>
WDTIPR0
WDTIPR1
<0>
<0>
0
1
0
1
882