UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 1016

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Instruction
Increment/
decrement
Shift
Group
2.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
3. cnt indicates the bit shift count.
Mnemonic
INC
DEC
INCW
DECW
SHR
SHRW
SHL
SHLW
SAR
SARW
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
When the program memory area is accessed.
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
register (CKC).
r
saddr
!addr16
[HL+byte]
ES:!addr16
ES: [HL+byte]
r
saddr
!addr16
[HL+byte]
ES:!addr16
ES: [HL+byte]
rp
saddrp
!addr16
[HL+byte]
ES:!addr16
ES: [HL+byte]
rp
saddrp
!addr16
[HL+byte]
ES:!addr16
ES: [HL+byte]
A, cnt
AX, cnt
A, cnt
B, cnt
C, cnt
AX, cnt
BC, cnt
A, cnt
AX, cnt
Operands
Bytes
Table 29-5. Operation List (12/17)
1
2
3
3
4
4
1
2
3
3
4
4
1
2
3
3
4
4
1
2
3
3
4
4
2
2
2
2
2
2
2
2
2
Note 1 Note 2
1
2
2
2
3
3
1
2
2
2
3
3
1
2
2
2
3
3
1
2
2
2
3
3
1
1
1
1
1
1
1
1
1
Clocks
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
r ← r + 1
(saddr) ← (saddr) + 1
(addr16) ← (addr16) + 1
(HL+byte) ← (HL+byte) + 1
(ES, addr16) ← (ES, addr16) + 1
((ES:HL) + byte) ← ((ES:HL) + byte) + 1
r ← r − 1
(saddr) ← (saddr) − 1
(addr16) ← (addr16) − 1
(HL+byte) ← (HL+byte) − 1
(ES, addr16) ← (ES, addr16) − 1
((ES:HL) + byte) ← ((ES:HL) + byte) − 1
rp ← rp + 1
(saddrp) ← (saddrp) + 1
(addr16) ← (addr16) + 1
(HL+byte) ← (HL+byte) + 1
(ES, addr16) ← (ES, addr16) + 1
((ES:HL) + byte) ← ((ES:HL) + byte) + 1
rp ← rp − 1
(saddrp) ← (saddrp) − 1
(addr16) ← (addr16) − 1
(HL+byte) ← (HL+byte) − 1
(ES, addr16) ← (ES, addr16) − 1
((ES:HL) + byte) ← ((ES:HL) + byte) − 1
(CY ← A
(CY ← AX
(CY ← A
(CY ← B
(CY ← C
(CY ← AX
(CY ← BC
(CY ← A
(CY ← AX
CPU
0
7
7
7
0
, A
, A
, B
, C
, A
0
0
15
, AX
15
) selected by the system clock control
, AX
, AX
, BC
m−1
m
m
m−1
m
← A
← B
m−1
← C
m−1
← A
← A
m
m
Operation
← AX
← AX
CHAPTER 29 INSTRUCTION SET
← BC
m−1
m−1
← AX
m−1
m
m
,
, A
, B
, A
, C
A
m
7
m−1
, AX
0
0
7
m−1
0
m
← 0) × cnt
← 0) × cnt
← 0) × cnt
← A
, AX
← 0) × cnt
, AX
, BC
15
7
← AX
15
) × cnt
0
0
← 0) × cnt
← 0) × cnt
← 0) × cnt
15
) × cnt
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
Flag
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
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