UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 838

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(3) Data ~ data ~ stop condition
Notes 1. To cancel a wait state, write “FFH” to IICA or set the WREL bit.
(When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3)
(communication status)
2. Make sure that the time between the rise of the SCL0 pin signal and the generation of the stop condition
3. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during slave transmission.
4. If a wait state during slave transmission is canceled by setting the WREL bit, the TRC bit will be cleared.
(8 or 9 clock wait)
(wait cancellation)
(wait cancellation)
(8 or 9 clock wait)
(transmit/receive)
(transmit/receive)
(ACK detection)
(ACK detection)
(communication
Master side
(ST detection)
(SP detection)
(ACK control)
(ACK control)
after a stop condition has been issued is at least 4.0
μ
Slave side
(ST trigger)
(SP trigger)
SCL0 (bus)
SDA0 (bus)
Bus line
(clock line)
(data line)
(interrupt)
(interrupt)
s when specifying fast mode.
INTIICA
INTIICA
WTIM
MSTS
WREL
status)
WREL
ACKD
WTIM
ACKE
ACKD
ACKE
MSTS
IICA
SPT
TRC
IICA
STD
SPD
TRC
STT
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Figure 15-33. Example of Slave to Master Communication
D
L
L
L
H
H
L
<8>
15
0
<10>
<9>
ACK
<12>
Note 1
<11>
Note 3
D
16
7
D
16
6
D
16
5
D
16
4
D
Stop conditon
16
μ
3
s when specifying standard mode and at least 0.6
CHAPTER 15 SERIAL INTERFACE IICA
D
16
2
D
16
1
<13>
D
16
0
Note 1
<14>
<15>
<16>
NACK
<17>
<18>
Note 4
Note 2
<19>
Notes 1, 4
838