UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 952

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
23.4.2 When used as interrupt
(1) When detecting level of supply voltage (V
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(a) When LVI default start function stopped is set (LVIOFF = 1)
• When starting operation
• When stopping operation
Figure 23-8 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this
timing chart correspond to <1> to <8> above.
Be sure to clear (0) the LVION bit by using a 1-bit memory manipulation instruction.
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
Mask the LVI interrupt (LVIMK = 1).
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
Clear bit 1 (LVIMD) of the LVIM register to 0 (generates interrupt signal when the level is detected)
Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection
Set bit 7 (LVION) of the LVIM register to 1 (enables LVI operation).
Use software to wait for the following periods of time (Total 210
Confirm that “supply voltage (V
Clear the interrupt request flag of LVI (LVIIF) to 0.
Release the interrupt mask flag of LVI (LVIMK).
Execute the EI instruction (when vector interrupts are used).
(V
(default value).
register (LVIS).
“supply voltage (V
the LVIM register.
• Operation stabilization time (10
• Minimum pulse width (200
DD
)) (default value).
DD
) < detection voltage (V
μ
s (MIN.))
DD
DD
) ≥ detection voltage (V
μ
)
s (MAX.))
LVI
)” when detecting the rising edge of V
CHAPTER 23 LOW-VOLTAGE DETECTOR
LVI
)” when detecting the falling edge of V
μ
s).
DD
, at bit 0 (LVIF) of
DD
, or
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