UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 550
UPD78F1009GB-GAH-AX
Manufacturer Part Number
UPD78F1009GB-GAH-AX
Description
MCU 16BIT 78K0R/KX3-L 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1009GB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Company:
Part Number:
UPD78F1009GB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
12.4.4 Setting watchdog timer interval interrupt
generated when 75% of the overflow time is reached.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be
Caution When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
Remark The watchdog timer continues counting even after INTWDTI is generated (until ACH is written to the
WDTINT
Remark If the overflow time is set to 2
0
1
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short, an
overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the STOP
mode release by an interval interrupt.
watchdog timer enable register (WDTE)). If ACH is not written to the WDTE register before the overflow time,
an internal reset signal is generated.
Interval interrupt is used.
Interval interrupt is generated when 75% of overflow time is reached.
<When window open period is 50%>
• Overflow time:
• Window close time:
• Window open time:
Window close time
Window open time
2
0 to 2
2
= 20.08 to 29.68 ms
10
10
/f
/f
IL
IL
(MAX.) = 2
10
Table 12-5. Setting of Watchdog Timer Interval Interrupt
(MIN.) × (1 − 0.5) to 2
/f
IL
(MIN.) × (1 − 0.5) = 0 to 2
10
/34.5 kHz (MAX.) = 29.68 ms
0 to 20.08 ms
20.08 to 29.68 ms
Use of Watchdog Timer Interval Interrupt
10
/f
50%
IL
, the window close time and open time are as follows.
10
/f
IL
10
(MAX.) = 2
/25.5 kHz (MIN.) × 0.5 = 0 to 20.08 ms
Setting of Window Open Period
0 to 10.04 ms
10.04 to 29.68 ms
10
/25.5 kHz (MIN.) × 0.5 to 2
75%
CHAPTER 12 WATCHDOG TIMER
None
0 to 29.68 ms
100%
10
/34.5 kHz (MAX.)
550
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