UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 1165

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Current
Version
(U20024E)
1st edition
Edition
Change of Figure 21-2. Timing of Reset by RESET Input
Change of Figure 21-4. Timing of Reset in STOP Mode by RESET Input
Change of Figure 22-2. Timing of Generation of Internal Reset Signal by Power-
on-Clear Circuit and Low-Voltage Detector (1/2)
Change of Note 4 in Figure 22-2. Timing of Generation of Internal Reset Signal
by Power-on-Clear Circuit and Low-Voltage Detector (2/2)
Change of Figure 22-3. Example of Software Processing After Reset Release
(1/2)
Change of Figure 23-11. Example of Software Processing After Reset Release
(1/2)
Change of 26.3 Communication Mode, and addition of Note
Addition of Note to Table 26-5. Communication Modes
Addition of Remark to 26.8 Flash Memory Programming by Self-Programming
Change of Figure 26-16. Flow of Self Programming (Rewriting Flash Memory)
Change of Table 27-1. Lists the Differences Between 1-line Mode and 2-line
Mode.
Change of description in 29.1.4 PREFIX instruction
Change of Table 29-5. Operation List
Change of high-level output current conditions, low-level output current conditions,
high-level input voltage conditions, low-level input voltage conditions, high-level
output voltage conditions, low-level output voltage conditions, high-level input leakage
current conditions, and low-level input leakage current conditions in 30.4 DC
Characteristics
Change of 30.6.1 (2) During communication at same potential (CSI mode)
(master mode, SCKp... internal clock output)
Change of 30.6.1 (3) During communication at same potential (CSI mode) (slave
mode, SCKp... external clock input)
Change of 30.6.1 (4) During communication at same potential (simplified I
mode)
Change of 30.6.1 (6) Communication at different potential (2.5 V, 3 V) (CSI mode)
(master mode, SCKp... internal clock
Change of 30.6.1 (7) Communication at different potential (2.5 V, 3 V) (CSI
mode) (slave mode, SCKp... external clock input)
Change of 30.6.1 (8) Communication at different potential (2.5 V, 3 V) (simplified
I
Change of 30.6.2 Serial interface IICA
Change of POC Circuit Timing in 30.6.7 POC circuit characteristics
Change of LVI Circuit Timing in 30.6.9 LVI circuit characteristics
Addition of chapter
2
C mode)
Description
APPENDIX B REVISION HISTORY
2
C
CHAPTER 21 RESET
FUNCTION
CHAPTER 22 POWER-
ON-CLEAR CIRCUIT
CHAPTER 23 LOW-
VOLTAGE DETECTOR
CHAPTER 26 FLASH
MEMORY
CHAPTER 27 ON-CHIP
DEBUG FUNCTION
CHAPTER 29
INSTRUCTION SET
CHAPTER 30
ELECTRICAL
SPECIFICATIONS
(78K0R/KC3-L,
78K0R/KD3-L,
78K0R/KE3-L)
CHAPTER 31
ELECTRICAL
SPECIFICATIONS
(78K0R/KF3-L,
78K0R/KG3-L)
Chapter
(3/6)
1165