UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 352

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: FFFA3H
Symbol
OSTS
Remark f
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS
Figure 7-8. Format of Oscillation Stabilization Time Select Register (OSTS)
OSTS2
7
0
0
0
0
0
1
1
1
1
After reset: 07H
2. Setting the oscillation stabilization time to 20
3. Change the setting of the OSTS register before setting the MSTOP bit of the clock
4. Do not change the value of the OSTS register during the X1 clock oscillation
5. The oscillation stabilization time counter counts up to the oscillation stabilization
6. The X1 clock oscillation stabilization wait time does not include the time until clock
X
: X1 clock oscillation frequency
register before executing the STOP instruction.
operation status control register (CSC) to 0.
stabilization time.
time set by the OSTS register.
In the following cases, set the oscillation stabilization time of the OSTS register to
the value greater than the count value which is to be checked by the OSTC register
after the oscillation starts.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
• If the STOP mode is entered and then released while the internal high-speed
oscillation starts (“a” below).
subsystem clock is being used as the CPU clock.
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
the OSTS register is set to the OSTC register after the STOP mode is released.)
OSTS1
6
0
0
0
1
1
0
0
1
1
X1 pin voltage
waveform
R/W
OSTS0
5
0
0
1
0
1
0
1
0
1
STOP mode release
2
2
2
2
2
2
2
2
8
9
10
11
13
15
17
18
/f
/f
/f
/f
/f
/f
/f
/f
X
X
X
X
X
X
X
X
4
0
a
Oscillation stabilization time selection
3
0
25.6
51.2
102.4
204.8
819.2
3.27 ms
13.11 ms
26.21 ms
CHAPTER 7 CLOCK GENERATOR
f
μ
X
μ
μ
s or less is prohibited.
s
s
μ
μ
μ
OSTS2
= 10 MHz
s
s
s
2
OSTS1
Setting prohibited
25.6
51.2
102.4
409.6
1.64 ms
6.55 ms
13.11 ms
1
f
X
μ
μ
s
s
μ
μ
= 20 MHz
s
s
OSTS0
0
352