UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 643

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
(Selective)
(Essential)
(Essential)
(Essential)
(Selective)
Changing setting of the SPSm register
Changing setting of the SDRmn register
Changing setting of the SMRmn register
Changing setting of the SCRmn register
Changing setting of the SOm register
Writing to the SSm register
Starting setting for resumption
Starting communication
Figure 14-39. Procedure for Resuming Master Reception
Clearing error flag
Port manipulation
Port manipulation
Enable clock output of the target channel
by setting a port register and a port mode
register.
Disable clock output of the target
channel by setting a port register and a
port mode register.
Re-set the register to change the operation
clock setting.
Re-set the register to change the
transfer baud rate setting (setting the
transfer clock by dividing the operation
clock (f
Re-set the register to change serial
mode register mn (SMRmn) setting.
Re-set the register to change serial
communication operation setting register
mn (SCRmn) setting.
Set the initial output level of the serial
clock (CKOmn).
If the FEF, PEF, and OVF flags remain
set, clear them using serial flag clear
trigger register mn (SIRmn).
Set the SSmn bit of the target channel to 1
and set the SEmn bit to 1 (to enable
operation).
Sets dummy data to the SIOp register (bits
7 to 0 of the SDRmn register) and start
communication.
MCK
)).
CHAPTER 14 SERIAL ARRAY UNIT
643