UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 1010

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Instruction
16-bit
data
transfer
8-bit
operation
Group
2.
3.
4.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
Mnemonic
MOVW
XCHW
ONEW
CLRW
ADD
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
When the program memory area is accessed.
Except rp = AX
Except r = A
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
register (CKC).
AX, ES:[HL + byte]
ES:[HL + byte], AX
AX, ES:word[B]
ES:word[B], AX
AX, ES:word[C]
ES:word[C], AX
AX, ES:word[BC]
ES:word[BC], AX
BC, ES:!addr16
DE, ES:!addr16
HL, ES:!addr16
AX, rp
AX
BC
AX
BC
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, ES:!addr16
A, ES:[HL]
A, ES:[HL + byte]
A, ES:[HL + B]
A, ES:[HL + C]
Operands
Note 3
Note 4
Bytes
Table 29-5. Operation List (6/17)
3
3
4
4
4
4
4
4
4
4
4
1
1
1
1
1
2
3
2
2
2
3
1
2
2
2
4
2
3
3
3
Note 1 Note 2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
2
2
2
2
2
Clocks
5
−
5
−
5
−
5
−
5
5
5
−
−
−
−
−
−
−
−
−
−
4
4
4
4
4
5
5
5
5
5
AX ← ((ES, HL) + byte)
((ES, HL) + byte) ← AX
AX ← ((ES, B) + word)
((ES, B) + word) ← AX
AX ← ((ES, C) + word)
((ES, C) + word) ← AX
AX ← ((ES, BC) + word)
((ES, BC) + word) ← AX
BC ← (ES, addr16)
DE ← (ES, addr16)
HL ← (ES, addr16)
AX ←→ rp
AX ← 0001H
BC ← 0001H
AX ← 0000H
BC ← 0000H
A, CY ← A + byte
(saddr), CY ← (saddr) + byte
A, CY ← A + r
r, CY ← r + A
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, CY ← A + (HL + byte)
A, CY ← A + (HL + B)
A, CY ← A + (HL + C)
A, CY ← A + (ES, addr16)
A,CY ← A + (ES, HL)
A,CY ← A + ((ES, HL) + byte)
A,CY ← A + ((ES, HL) + B)
A,CY ← A + ((ES, HL) + C)
CPU
) selected by the system clock control
Operation
CHAPTER 29 INSTRUCTION SET
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Flag
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
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