UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 578

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(8) Interrupt request flag (ADIF)
(9) Conversion results just after A/D conversion start
(10) A/D conversion result register (ADCR, ADCRH) read operation
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the
pre-change analog input may be set just before the ADS register rewrite. Caution is therefore required since, at this
time, when ADIF flag is read immediately after the ADS register rewrite, ADIF flag is set despite the fact A/D
conversion for the post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF flag before the A/D conversion operation is resumed.
Remark n = 0 to 9, m = 0 to 9:
The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS
bit is set to 1 within 1
interrupt request (INTAD) and removing the first conversion result.
When a write operation is performed to the A/D converter mode register (ADM), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of the ADCR and ADCRH registers may
become undefined. Read the conversion result following conversion completion before writing to the ADM, ADS, or
ADPC register. Using a timing other than the above may cause an incorrect conversion result to be read.
A/D conversion
n = 0 to 10, m = 0 to 10: 78K0R/KD3-L
n = 0 to 11, m = 0 to 11: 78K0R/KE3-L, 78K0R/KF3-L
n = 0 to 11, m = 0 to 15: 78K0R/KG3-L
ADCR
ADIF
ADS rewrite
(start of ANIn conversion)
Figure 13-23. Timing of A/D Conversion End Interrupt Request Generation
μ
s after the ADCE bit was set to 1. Take measures such as polling the A/D conversion end
ANIn
78K0R/KC3-L (40-pin, 44-pin), 78K0R/KC3-L (48-pin)
ADS rewrite
(start of ANIm conversion)
ANIn
ANIn
ANIm
ANIn
ADIF is set but ANIm conversion
has not ended.
CHAPTER 13 A/D CONVERTER
ANIm
ANIm
ANIm
578