UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 155

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(3) Stack pointer (SP)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(d) Auxiliary carry flag (AC)
(e) In-service priority flags (ISP1, ISP0)
(f) Carry flag (CY)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be set as
the stack area.
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the
stack memory.
Each stack operation saves data as shown in Figure 4-19.
Caution 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.
This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests
specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PRn0L, PRn0H,
PRn1L, PRn1H, PRn2L, PRn2H) (see 18.3 (3)) can not be acknowledged. Actual request acknowledgment is
controlled by the interrupt enable flag (IE).
Remark n = 0, 1
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon
rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
2. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as a stack area.
3. While using the self-programming function, the area FFE20H to FFEFFH cannot be used as stack
using the stack.
memory. Furthermore, the areas of FF300H to FF6FFH and FDF00H to FE2FFH also cannot be
used with the
78F1028, 78F1029, and 78F1030, respectively.
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
15
μ
PD78F1003, 78F1006 and 78F1009, and
Figure 4-22. Format of Stack Pointer
CHAPTER 4 CPU ARCHITECTURE
μ
PD78F1012 and 78F1014, 78F1027,
0
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