UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 403

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F00F0H
(1) Peripheral enable registers 0, 2 (PER0, PER2)
Symbol
PER0
These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When the timer array unit is used, be sure to set the following bits to 1.
The PER0 and PER2 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
• 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L
• 78K0R/KF3-L, 78K0R/KG3-L
Remark m = 0, 1
Cautions 1. When setting the timer array unit m, be sure to set the TAU0EN and TAU1EN bits to 1
When timer array unit 0 is used → Bit 0 (TAU0EN) of the PER2 register
When timer array unit 0 is used → Bit 0 (TAU0EN) of the PER0 register
When timer array unit 1 is used → Bit 1 (TAU1EN) of the PER0 register
Figure 8-8. Format of Peripheral Enable Register 0 (PER0) (78K0R/KF3-L, 78K0R/KG3-L)
TAUmEN
RTCEN
<7>
0
1
After reset: 00H
2. Be sure to clear bit 6 to 0.
Stops supply of input clock.
• SFR used by the timer array unit m cannot be written.
• The timer array unit m is in the reset status.
Supplies input clock.
• SFR used by the timer array unit m can be read/written.
first. If TAU0EN, TAU1EN = 0, writing to a control register of timer array unit m is ignored,
and all read values are default values (except for the timer input select register m (TISm),
input switch control register (ISC), noise filter enable registers 1, 2 (NFEN1, NFEN2), port
mode registers 0, 1, 3, 4, 6, 13, 14 (PM0, PM1, PM3, PM4, PM6, PM13, PM14), and port
registers 0, 1, 3, 4, 6, 13, 14 (P0, P1, P3, P4, P6, P13, P14)).
6
0
R/W
ADCEN
<5>
Control of timer array unit m input clock (m = 0, 1)
IICAEN
<4>
SAU1EN
<3>
CHAPTER 8 TIMER ARRAY UNIT
SAU0EN
<2>
TAU1EN
<1>
TAU0EN
<0>
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