UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 527

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L CHAPTER 10 COMPARATORS/PROGRAMMABLE GAIN AMPLIFIERS (78K0R/KC3-L, KD3-L, KE3-L only)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Notes 1. If OAEN = 1 (bit 7 of the programmable gain amplifier control register (OAM)) and the CnEN bit is set to
Cautions 1. Rewrite the CnINV and CnDFS2 to CnDFS0 bits after setting the comparator output to the
Remarks 1. f
2. There is no positive-side input pin for comparator 1 in the 78K0R/KC3-L (40-pin). Only the signal output
3. An interrupt will occur if the CnINV bit is set (CnINV = 1) while operation is stopped (CnEN = 0) or when
1, a programmable gain amplifier output signal will be input to the positive-side input of comparator n.
from the programmable gain amplifier can be used for the input voltage.
output is prohibited (CnOE = 0). It is therefore necessary to mask the interrupt (CMPMKn = 1), and then
t reverse output (CnINV = 1), clear the interrupt request flag (CMPIFn = 0), and then unmask the interru
pt (CMPMKn = 0). While reverse output is in progress, be sure to mask the interrupt (CMPMKn = 1) bef
ore stopping operation (CnEN = 0) or prohibiting output (CnOE = 0).
2. n = 0, 1
2. With the noise elimination width, an extra CPU clock (f
3. To operate the comparator in combination with a programmable gain amplifier, set the
4. The negative-side external pin input of the comparator will be cutoff when the CnVRE bit of
5. Enable interrupt signals after setting CnEN = 1 and then waiting for 1
enable operation (CnEN = 1) and output (CnOE = 1). After operation and output have been enabled, se
disabled state (CnOE = 0).
value.
(Example: When f
ns)
operation of the comparator after setting the operation of the programmable gain amplifier
(see Figure 10-10 and Figure 10-11).
the comparator n internal reference voltage selection register (CnRVM) is set (1), regardless
of the value that enables or disables the comparator operation (CnEN bit).
CLK
: CPU or peripheral hardware clock frequency
CLK
= 20 MHz, CnDFS2 to CnDFS0 = 001, noise elimination width = 250 to 300
CLK
) may be eliminated from the setting
μ
s by software.
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