UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 412

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F01B2H, F01B3H
Address: F01DAH, F01DBH
(6) Timer channel start register m (TSm)
Symbol
Symbol
TS0
TS1
The TSm register is a trigger register that is used to clear timer/counter register mn (TCRmn) and start the counting
operation of each channel.
When a bit (TSmn) of this register is set to 1, the corresponding bit (TEmn) of timer channel enable status register
m (TEm) is set to 1. The TSmn bit is immediately cleared when operation is enabled (TEmn = 1), because it is a
trigger bit.
The TSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TSm register can be set with a 1-bit or 8-bit memory manipulation instruction with TSmL.
Reset signal generation clears this register to 0000H.
Caution Be sure to clear bits 15 to 8 of the TS0 register and bits 15 to 4 of the TS1 register to “0”
Remarks 1. When the TSm register is read, 0 is always read.
TSm
15
15
n
0
1
0
0
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
No trigger operation
The TEmn bit is set to 1 and the count operation becomes enabled.
The TCRmn register count operation start in the count operation enabled state varies depending on each
operation mode (see Table 8-4).
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
14
14
0
0
After reset: 0000H
13
13
After reset: 0000H
Figure 8-14. Format of Timer Channel Start register m (TSm)
0
0
12
12
0
0
11
11
0
0
R/W
R/W
10
10
0
0
Operation enable (start) trigger of channel n
9
0
9
0
8
0
8
0
TS07 TS06 TS05 TS04 TS03 TS02 TS01 TS00
mn = 00 to 07, 10 to 13
7
7
0
6
6
0
CHAPTER 8 TIMER ARRAY UNIT
5
5
0
4
4
0
TS13 TS12 TS11 TS10
3
3
2
2
1
1
0
0
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