UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 778

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
15.5 I
Figure 15-14 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I
bus’s serial data bus.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device that
receives 8-bit data).
level period can be extended and a wait can be inserted.
15.5.1 Start conditions
start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device when
starting a serial transfer. When the device is used as a slave, start conditions can be detected.
detected (SPD: Bit 0 of the IICA status register (IICS) = 1). When a start condition is detected, bit 1 (STD) of the IICS
register is set (1).
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The following section describes the I
The master device generates the start condition, slave address, and stop condition.
The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0 pin low
A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level. The
A start condition is output when bit 1 (STT) of IICA control register 0 (IICCTL0) is set (1) after a stop condition has been
2
C Bus Definitions and Control Methods
SDA0
SCL0
Start
condition
Figure 15-14. I
Address R/W ACK
1-7
SDA0
SCL0
2
C bus’s serial data communication format and the signals used by the I
Figure 15-15. Start Conditions
8
H
2
C Bus Serial Data Transfer Timing
9
Data
1-8
ACK
9
CHAPTER 15 SERIAL INTERFACE IICA
Data
1-8
ACK
9
Stop
condition
2
C bus.
778
2
C