UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 798

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(1) Master operation in single-master system
Note Release (SCL0 and SDA0 pins = high level) the I
Remark
that is communicating. If EEPROM is outputting a low level to the SDA0 pin, for example, set the SCL0 pin in
the output port mode, and output a clock pulse from the output port until the SDA0 pin is constantly at high level.
Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
No
No
Figure 15-28. Master Operation in Single-Master System
Setting STCEN, IICRSV = 0
ACKE = WTIM = SPIE = 1
IICCTL0 ← 0XX111XXB
IICCTL0 ← 1XX111XXB
IICWL, IICWH ← XXH
Initializing I
interrupt occurs?
interrupt occurs?
interrupt occurs?
End of transfer?
SVA ← XXH
STCEN = 1?
Writing IICA
Writing IICA
Setting port
IICF ← 0XH
Setting port
ACKD = 1?
ACKD = 1?
TRC = 1?
INTIICA
INTIICA
IICE = 1
SPT = 1
STT = 1
INTIICA
Restart?
START
No
Yes
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
C bus
Note
Waits for detection of the stop condition.
Yes
No
No
No
No
No
No
Prepares for starting communication
(generates a stop condition).
Starts transmission.
Waits for data transmission.
Prepares for starting communication
(generates a start condition).
Starts communication
(specifies an address and transfer
direction).
Waits for detection of acknowledge.
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 15.3 (8) Port mode register 6 (PM6)).
Sets a transfer clock.
Sets a local address.
Sets a start condition.
Set the port from input mode to output mode and enable the output of the I
(see 15.3 (8) Port mode register 6 (PM6)).
SPT = 1
END
2
C bus in conformance with the specifications of the product
WTIM = WREL = 1
interrupt occurs?
CHAPTER 15 SERIAL INTERFACE IICA
interrupt occurs?
End of transfer?
Reading IICA
WREL = 1
ACKE = 0
ACKE = 1
WTIM = 0
INTIICA
INTIICA
Yes
Yes
Yes
No
No
No
Waits for data
reception.
Starts reception.
Waits for detection
of acknowledge.
2
C bus
798