UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 373

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
7.6.4 Example of setting X1 oscillation clock
oscillation clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by
using the operation speed mode control register (OSMC), clock operation mode control register (CMC), and clock
operation status control register (CSC) and wait for oscillation to stabilize by using the oscillation stabilization time counter
status register (OSTC). After the oscillation stabilizes, set the X1 oscillation clock to f
register (CKC).
byte.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
After a reset release, the CPU/peripheral hardware clock (f
Set the frequency of the internal oscillation clock to be supplied immediately after releasing reset by using the option
[Option byte setting]
Set address 000C1H to FBH.
[Register settings] Set the register in the order of <1> to <5> below.
<1> Use the OSMC register to set the frequency of the CPU/peripheral hardware.
<2> Set (1) the OSCSEL bit of the CMC register to operate the X1 oscillator.
<3> Clear (0) the MSTOP bit of the CSC register to start oscillating the X1 oscillator.
Note
Note
Note
(000C1H)
OSMC
Option
CMC
CSC
byte
RTCLPC bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), be sure to clear
RTCLPC bit to 0.
OSCSELS bit is not provided in the 78K0R/KC3-L (40-pin).
XTSTOP bit is not provided in the 78K0R/KC3-L (40-pin).
LVIOFF bit: Set this bit to 0 to turn on the LVI by default when releasing the power-on-reset.
FRQSEL2 and FRQSEL1 bits: Set the FRQSEL2 and FRQSEL1 bits to 1 and 0, respectively, to set the
FSEL bit: Set this bit to 0 if the CPU/peripheral hardware clock is 10 MHz or less.
RTCLPC bit
AMPH bit: Set this bit to 0 if the X1 oscillation clock is 10 MHz or less.
OSCSELS bit
AMPHS0 and AMPHS1 bits: These bits are used to specify the oscillation mode of the XT1 oscillator.
XTSTOP bit
RTCLPC
MSTOP
EXCLK
7
1
7
0
7
0
7
0
Note
Note
Note
Note
: Set this bit to 0 to oscillate the XT1 oscillator.
XTSTOP
: Set this bit to 1 to operate only the watch in sub-HALT mode (ultra-low current
: Set this bit to 1 to set P122 and P123 to XT1 oscillation mode.
OSCSEL
consumption).
6
1
6
0
6
1
6
1
Note
internal oscillation clock frequency to 1 MHz.
1
0
0
0
5
5
5
5
OSCSELS
4
1
4
4
4
0
0
0
Note
CLK
) always starts operating with the internal high-speed
3
1
3
0
3
0
3
0
CHAPTER 7 CLOCK GENERATOR
FRQSEL2
AMPHS1
2
0
2
0
2
0
2
0
CLK
by using the system clock control
FRQSEL1
AMPHS0
FLPC
1
1
1
0
1
0
1
0
HIOSTOP
LVIOFF
AMPH
FSEL
0
1
0
1
0
1
0
0
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