UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 510

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UPD78F1009GB-GAH-AX

Manufacturer Part Number
UPD78F1009GB-GAH-AX
Description
MCU 16BIT 78K0R/KX3-L 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet

Specifications of UPD78F1009GB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1009GB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
78K0R/Kx3-L
9.4.2 Shifting to STOP mode after starting operation
INTRTC interrupt has occurred.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
• Shifting to STOP mode when at least two subsystem clocks (f
• Checking by polling the RWST bit to become 1, after setting the RTCE bit to 1 and then setting the RWAIT bit to 1.
Perform one of the following processing when shifting to STOP mode immediately after setting the RTCE bit to 1.
However, after setting the RTCE bit to 1, this processing is not required when shifting to STOP mode after the first
Figure 9-19, Example 1).
Afterward, setting the RWAIT bit to 0 and shifting to STOP mode after checking again by polling that the RWST bit
has become 0 (see Figure 9-19, Example 2).
Waiting at least for 2
STOP mode
f
RTCE = 1
SUB
clocks
Figure 9-19. Procedure for Shifting to STOP Mode After Setting RTCE bit to 1
Example 1
Sets to counter operation
start
Shifts to STOP mode
No
No
SUB
RWST = 1 ?
RWST = 0 ?
STOP mode
RWAIT = 1
RWAIT = 0
RTCE = 1
) have elapsed after setting the RTCE bit to 1 (see
Yes
Yes
CHAPTER 9 REAL-TIME COUNTER
Example 2
Sets to counter operation
start
Checks the counter wait status
Sets the counter operation
Sets to stop the SEC to YEAR
counters, reads the counter
value, write mode
Shifts to STOP mode
510

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