UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 772

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(5) IICA control register 1 (IICCTL1)
Address: F0231H
IICCTL1
Symbol
This register is used to set the operation mode of I
The IICCTL1 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD and DAD
bits are read-only.
Set the IICCTL1 register, except the WUP bit, while operation of I
0 (IICCTL0) is 0).
Reset signal generation clears this register to 00H.
Notes 1. Bits 4 and 5 are read-only.
To shift to STOP mode when WUP = 1, execute the STOP instruction at least three clocks after setting (1) the
WUP bit (see Figure 15-22 Flow When Setting WUP = 1).
Clear (0) the WUP bit after the address has matched or an extension code has been received. The subsequent
communication can be entered by the clearing (0) WUP bit. (The wait must be released and transmit data must
be written after the WUP bit has been cleared (0).)
The interrupt timing when the address has matched or when an extension code has been received, while WUP
= 1, is identical to the interrupt timing when WUP = 0. (A delay of the difference of sampling by the clock will
occur.) Furthermore, when WUP = 1, a stop condition interrupt is not generated even if the SPIE bit is set to 1.
When WUP = 0 is set by a source other than an interrupt from serial interface IICA, operation as the master
device cannot be performed until the subsequent start condition or stop condition is detected. Do not output a
start condition by setting (1) the STT bit, without waiting for the detection of the subsequent start condition or
stop condition.
Condition for clearing (WUP = 0)
• Cleared by instruction (after address match or
extension code reception)
WUP
WUP
7
0
1
2. The status of the IICA status register (IICS) must be checked and the WUP bit must be set
SDA0
SCL0
After reset: 00H
during the period shown below.
Stops operation of address match wakeup function in STOP mode.
Enables operation of address match wakeup function in STOP mode.
Figure 15-9. Format of IICA Control Register 1 (IICCTL1) (1/2)
6
0
Check the IICS operation status and set
WUP during this period.
CLD
<5>
R/W
Note 1
<1>
DAD
<4>
The maximum time from reading IICS to setting
WUP is the period from <1> to <2>.
2
Control of address match wakeup
C and detect the statuses of the SCL0 and SDA0 pins.
A6
SMC
<3>
A5
Condition for setting (WUP = 1)
• Set by instruction (when the MSTS, EXC, and COI
bits are “0”, and the STD bit also “0” (communication
not entered))
A4
2
C is disabled (bit 7 (IICE) of IICA control register
CHAPTER 15 SERIAL INTERFACE IICA
DFC
<2>
A3
Note 2
A2
1
0
A1
A0
0
0
<2>
R/W
772