UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 554

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
13.3 Registers Used in A/D Converter
(1) Peripheral enable register 0 (PER0)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F00F0H
The A/D converter uses the following seven registers.
• Peripheral enable register 0 (PER0)
• A/D converter mode register (ADM)
• A/D port configuration register (ADPC)
• Analog input channel specification register (ADS)
• Port mode registers 2, 15, 8
• 10-bit A/D conversion result register (ADCR)
• 8-bit A/D conversion result register (ADCRH)
Symbol
PER0
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Cautions 1. When setting the A/D converter, be sure to set the ADCEN bit to 1 first. If ADCEN = 0, writing
Note Port mode register 8 is set only in the 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L.
Notes 1. That is not provided in 40-pin product of the 78K0R/KC3-L.
RTCEN
2. That is not provided in 40-pin and 44-pin products of the 78K0R/KC3-L.
3. 78K0R/KF3-L and 78K0R/KG3-L only.
ADCEN
2. Be sure to clear the following bits to 0.
<7>
0
1
After reset: 00H
to a control register of the A/D converter is ignored, and, even if the register is read, only the
default value is read (except for port mode registers 2, 15, and 8 (PM2, PM15, and PM8)).
48-pin product of the 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: bits 0, 1, 3, 6
44-pin product of the 78K0R/KC3-L:
40-pin product of the 78K0R/KC3-L:
78K0R/KF3-L, 78K0R/KG3-L:
Note 1
Stops input clock supply.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
Enables input clock supply.
• SFR used by the A/D converter can be read/written.
Figure 13-2. Format of Peripheral Enable Register 0 (PER0)
6
0
Note
R/W
(PM2, PM15, PM8
ADCEN
<5>
Control of A/D converter input clock supply
IICAEN
Note
<4>
)
Note 2
bits 0, 1, 3, 4, 6
bits 0, 1, 3, 4, 6, 7
bit 6
SAU1EN
<3>
Note 3
SAU0EN
<2>
CHAPTER 13 A/D CONVERTER
TAU1EN
<1>
Note 3
TAU0EN
<0>
Note 3
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