UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 850

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
17.2 Configuration of DMA Controller
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The DMA controller includes the following hardware.
(1) DMA SFR address register n (DSAn)
Address registers
Count register
Control registers
Address: FFFB0H (DSA0), FFFB1H (DSA1)
This is an 8-bit register that is used to set an SFR address that is the transfer source or destination of DMA
channel n.
Set the lower 8 bits of the SFR addresses FFF00H to FFFFFH.
This register is not automatically incremented but fixed to a specific value.
In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address.
The DSAn register can be read or written in 8-bit units. However, it cannot be written during DMA transfer.
Reset signal generation clears this register to 00H.
Remark
DSAn
Item
n: DMA channel number (n = 0, 1)
7
6
Figure 17-1. Format of DMA SFR Address Register n (DSAn)
• DMA SFR address registers 0, 1 (DSA0, DSA1)
• DMA RAM address registers 0, 1 (DRA0, DRA1)
• DMA byte count registers 0, 1 (DBC0, DBC1)
• DMA mode control registers 0, 1 (DMC0, DMC1)
• DMA operation control register 0, 1 (DRC0, DRC1)
5
Table 17-1. Configuration of DMA Controller
4
3
After reset: 00H
2
1
0
Configuration
R/W
CHAPTER 17 DMA CONTROLLER
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