UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 605

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F0108H, F0109H (SIR00) to F010EH, F010FH (SIR03),
(6) Serial flag clear trigger register mn (SIRmn)
Symbol
SIRmn
The SIRmn register is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn,
OVFmn) of serial status register mn is cleared to 0. Because the SIRmn register is a trigger register, it is cleared
immediately when the corresponding bit of the SSRmn register is cleared.
The SIRmn register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SIRmn register can be set with an 8-bit memory manipulation instruction with SIRmnL.
Reset signal generation clears the SIRmn register to 0000H.
Caution Be sure to clear bits 15 to 3 to “0”.
Remarks 1. m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 3)
F0148H, F0149H (SIR10) to F014EH, F014FH (SIR13),
F0204H, F0205H (SIR20) , F0206H, F0207H (SIR21)
OVC
FEC
PEC
Tmn
Tmn
Tmn
15
0
1
0
1
0
1
0
2. When the SIRmn register is read, 0000H is always read.
Not cleared
Clears the FEFmn bit of the SSRmn register to 0.
Not cleared
Clears the PEFmn bit of the SSRmn register to 0.
Not cleared
Clears the OVFmn bit of the SSRmn register to 0.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L
78K0R/KF3-L
78K0R/KG3-L
78K0R/KG3-L
14
0
Figure 14-10. Format of Serial Flag Clear Trigger Register mn (SIRmn)
13
0
12
0
μ
μ
μ
μ
PD78F1010, 78F1011, 78F1012 :
PD78F1027, 78F1028 :
PD78F1013, 78F1014 :
PD78F1029, 78F1030 :
11
0
10
Clear trigger of overrun error flag of channel n
0
Clear trigger of parity error flag of channel n
Clear trigger of framing error of channel n
9
0
8
0
After reset: 0000H
7
0
6
0
mn = 00 to 03
mn = 00 to 03, 10 to 13
mn = 00 to 03, 10 to 13, 20, 21
mn = 00 to 03, 10 to 13
mn = 00 to 03, 10 to 13, 20, 21
CHAPTER 14 SERIAL ARRAY UNIT
5
0
R/W
4
0
3
0
FEC
Tmn
2
PEC
Tmn
1
OVC
Tmn
0
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