UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 16

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 17 DMA CONTROLLER ..................................................................................................... 849
CHAPTER 18 INTERRUPT FUNCTIONS............................................................................................. 870
CHAPTER 19 KEY INTERRUPT FUNCTION ..................................................................................... 905
CHAPTER 20 STANDBY FUNCTION .................................................................................................. 908
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
17.1 Functions of DMA Controller .................................................................................................. 849
17.2 Configuration of DMA Controller ............................................................................................ 850
17.3 Registers Controlling DMA Controller ................................................................................... 853
17.4 Operation of DMA Controller................................................................................................... 857
17.5 Example of Setting of DMA Controller ................................................................................... 859
17.6 Cautions on Using DMA Controller ........................................................................................ 868
18.1 Interrupt Function Types ......................................................................................................... 870
18.2 Interrupt Sources and Configuration ..................................................................................... 870
18.3 Registers Controlling Interrupt Functions (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L). 876
18.4 Registers Controlling Interrupt Functions (78K0R/KF3-L, 78K0R/KG3-L).......................... 886
18.5 Interrupt Servicing Operations ............................................................................................... 897
19.1 Functions of Key Interrupt ...................................................................................................... 905
19.2 Configuration of Key Interrupt ................................................................................................ 905
19.3 Register Controlling Key Interrupt ......................................................................................... 907
20.1 Standby Function and Configuration ..................................................................................... 908
17.4.1 Operation procedure .................................................................................................................... 857
17.4.2 Transfer mode .............................................................................................................................. 858
17.4.3 Termination of DMA transfer ........................................................................................................ 858
17.5.1 CSI consecutive transmission ...................................................................................................... 859
17.5.2 Consecutive capturing of A/D conversion results ......................................................................... 861
17.5.3 UART consecutive reception + ACK transmission........................................................................ 863
17.5.4 Holding DMA transfer pending by DWAITn bit ............................................................................. 865
17.5.5 Forced termination by software .................................................................................................... 866
18.5.1 Maskable interrupt request acknowledgment ............................................................................... 897
18.5.2 Software interrupt request acknowledgment ................................................................................ 900
18.5.3 Multiple interrupt servicing............................................................................................................ 900
18.5.4 Interrupt request hold ................................................................................................................... 904
20.1.1 Standby function........................................................................................................................... 908
20.1.2 Registers controlling standby function.......................................................................................... 909
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