UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 700

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
14.6.2 UART reception
stop synchronization).
odd- and even-numbered channels must be set.
Notes 1. 78K0R/KF3-L, 78K0R/KG3-L only.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remarks 1. f
UART reception is an operation wherein the 78K0R/Kx3-L asynchronously receives data from another device (start-
For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the
Target channel
Pins used
Interrupt
Error interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
2. UART4 is only mounted in the 78K0R/KF3-L (
3. Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
UART
78F1030).
specifications (see CHAPTER 30
78K0R/KE3-L), CHAPTER 31 ELECTRICAL SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L)).
2. m: Unit number (m = 0 to 2), n: Channel number (n = 1, 3)
f
78K0R/KG3-L (
78K0R/KG3-L (
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L (
78K0R/KF3-L (
MCK
CLK
:
:
Operation clock frequency of target channel
System clock frequency
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
RxD0
INTSR0
INTSRE0
• Framing error detection flag (FEFmn)
• Parity error detection flag (PEFmn)
• Overrun error detection flag (OVFmn)
5, 7 or 8 bits
Max. f
Forward output (default: high level)
Reverse output (default: low level)
The following selectable
• No parity bit (no parity check)
• Appending 0 parity (no parity check)
• Appending even parity
• Appending odd parity
Appending 1 bit
MSB or LSB first
Channel 1 of
μ
μ
μ
μ
PD78F1010, 78F1011, 78F1012):
PD78F1027, 78F1028):
PD78F1013, 78F1014):
PD78F1029, 78F1030):
UART0
MCK
SAU0
/6 [bps] (SDRmn [15:9] = 2 or more), Min. f
RxD1
INTSR1
INTSRE1
Channel 3 of
UART1
SAU0
ELECTRICAL SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L,
μ
PD78F1027, 78F1028) and 78K0R/KG3-L (
RxD2
INTSR2
INTSRE2
Channel 1 of
mn = 01, 03
mn = 01, 03, 11, 13
mn = 01, 03, 11, 13, 21
mn = 01, 03, 11, 13
mn = 01, 03, 11, 13, 21
UART2
SAU1
CLK
Note 1
/(2 × 2
CHAPTER 14 SERIAL ARRAY UNIT
11
× 128) [bps]
RxD3
INTSR3
INTSRE3
Channel 3 of
UART3
SAU1
Note 1
Note 3
RxD4
INTSR4
INTSRE4
Channel 1 of
UART4
μ
SAU2
PD78F1029,
Note 2
700