UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 424

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F01BEH, F01BFH
Address: F01E6, F01E7H
(12) Timer output mode register m (TOMm)
Symbol
Symbol
TOM0
TOM1
Caution Be sure to clear bits 15 to 8 of the TOM0 register and bits 15 to 4 of the TOM1 register to “0”.
Remark
Note
The TOMm register is used to control the timer output mode of each channel.
When a channel is used for the independent channel operation function, set the corresponding bit of the channel
to be used to 0.
When a channel is used for the simultaneous channel operation function (PWM output, one-shot pulse output, or
multiple PWM output), set the corresponding bit of the master channel to 0 and the corresponding bit of the slave
channel to 1.
The setting of each channel n by this register is reflected at the timing when the timer output signal is set or reset
while the timer output is enabled (TOEmn = 1).
The TOMm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOMm register can be set with an 8-bit memory manipulation instruction with TOMmL.
Reset signal generation clears this register to 0000H.
TOM
mn
15
15
0
1
0
0
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
p: Slave channel number
When m = 0: Master channel n = 0, 2, 4, 6, n < p ≤ 7
When m = 1: Master channel n = 0, 2, n < p ≤ 3
(where p is a consecutive integer greater than n)
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as
the slave channel.
Master channel output mode (to produce toggle output by timer interrupt request signal (INTTMmn))
Slave channel output mode (output is set by the timer interrupt request signal (INTTMmn) of the master
channel, and reset by the timer interrupt request signal (INTTMmp) of the slave channel)
14
14
0
0
After reset: 0000H
Figure 8-25. Format of Timer Output Mode register m (TOMm)
After reset: 0000H
13
13
0
0
12
12
0
0
11
11
0
0
Note
R/W
R/W
10
10
0
0
Control of timer output mode of channel n
9
0
9
0
8
0
8
0
mn = 00 to 07, 10 to 13
TOM
07
7
7
0
TOM
06
6
6
0
TOM
05
CHAPTER 8 TIMER ARRAY UNIT
5
5
0
TOM
04
4
4
0
TOM
TOM
03
13
3
3
TOM
TOM
02
12
2
2
TOM
TOM
01
11
1
1
TOM
TOM
00
10
0
0
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