UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 456

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
8.7.3 Operation as frequency divider (channel 0 of 78K0R/KD3-L, KE3-L, KF3-L. KG3-L only)
from the TO00 pin.
value of timer data register 00 (TDR00) when the TI00 valid edge is detected.
the MD000 bit of timer mode register 00 (TMR00) is 1, INTTM00 is output and TO00 is toggled.
At the same time, the TCR00 register loads the value of the TDR00 register again, and continues counting.
period of the TO00 output.
count period.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the result
The divided clock frequency output from TO00 can be calculated by the following expression.
Timer/counter register 00 (TCR00) operates as a down counter in the interval timer mode.
After the channel start trigger bit (TS00) of timer channel start register 0 (TS0) is set to 1, the TCR00 register loads the
If the MD000 bit of timer mode register 00 (TMR00) is 0 at this time, INTTM00 is not output and TO00 is not toggled. If
After that, the TCR00 register counts down at the valid edge of the TI00 pin. When TCR00 = 0000H, it toggles TO00.
If detection of both the edges of the TI00 pin is selected, the duty factor error of the input clock affects the divided clock
The period of the TO00 output clock includes a sampling error of one period of the operation clock.
The TDR00 register can be rewritten at any time. The new value of the TDR00 register becomes valid during the next
• When rising edge/falling edge is selected:
• When both edges are selected:
Clock period of TO00 output = Ideal TO00 output clock period ± Operation clock period (error)
Divided clock frequency = Input clock frequency/{(Set value of TDR00 + 1) × 2}
Divided clock frequency ≅ Input clock frequency/(Set value of TDR00 + 1)
TI00 pin
TS00
detection
Edge
Figure 8-49. Block Diagram of Operation as Frequency Divider
register 00 (TCR00)
register 00 (TDR00)
Timer counter
Timer data
CHAPTER 8 TIMER ARRAY UNIT
controller
Output
TO00 pin
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