UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 749

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note 1
SE
02
0
1
0
1
0
78K0R/Kx3-L
Notes 1. Serial channel enable register 0 (SE0) is a read-only status register which is set using serial channel statrt
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remark X: Don’t care
022
MD
0
0
1
0
0
1
2. When channel 3 of unit 0 is set to UART1 reception, this pin becomes an RxD1 function pin (refer to Table 14-
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 14.3 (12) Serial output register
5. When using UART1 transmission and reception in a pair, set channel 3 of unit 0 to UART1 reception (refer to
6. Set the CKO02 bit to 1 before a start condition is generated. Clear the SO02 bit from 1 to 0 when the start
7. Set the CKO02 bit to 1 before a stop condition is generated. Clear the SO02 bit from 0 to 1 when the stop
021
MD
0
1
0
0
1
0
12). In this case, operation stop mode or UART1 transmission must be selected for channel 2 of unit 0.
m (SOm).
Table 14-12).
condition is generated.
condition is generated.
register 0 (SS0) and serial channel stop register 0 (ST0).
SOE
02
0
0
1
1
0
1
1
1
0
1
1
1
0
Note 4
Note 4
Note 4
Note 4
Note 4
Note 6
Note 4
Note 4
Note 4
Note 7
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
SO
02
1
1
1
Note 4
Note 4
Note 4
Note 6
Note 4
Note 4
Note 4
Note 7
CKO
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
02
1
1
1
1
1
TXE
02
Table 14-11. Relationship between register settings and pins
0
0
1
1
0
1
1
1
0
1
0
1
1
0
0
1
0
(Channel 2 of unit 0: CSI10, UART1 transmission, IIC10)
RXE
02
0
1
0
1
1
0
1
0
0
0
1
0
0
1
0
0
1
Note 3
Note 3
PM
04
1
1
1
0
0
0
0
0
0
0
0
×
×
Note 3
Note 3
P04 PM03
×
×
×
×
1
1
1
×
1
1
1
1
1
Note 3
Note 3
Note 3
Note 3
Note 2
×
1
×
1
1
×
1
×
0
0
0
0
0
Note 3
Note 3
Note 3
Note 3
Note 2
P03
×
×
×
×
×
×
×
×
1
1
1
1
1
PM02 P02
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
×
×
0
0
×
0
0
0
×
×
×
×
×
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
×
×
1
1
×
1
1
1
×
×
×
×
×
transmission /reception
transmission /reception
transmission
IIC10 address field
Operation mode
Operation stop
start condition
Master CSI10
Master CSI10
stop condition
Slave CSI10
Slave CSI10
transmission
transmission
transmission
Master CSI10
transmission
Slave CSI10
IIC10 data
IIC10 data
reception
reception
reception
UART1
mode
IIC10
IIC10
CHAPTER 14 SERIAL ARRAY UNIT
Note 5
SCL10/P04
(output)
(output)
(output)
SCK10/
SCK10
SCK10
SCK10
SCK10
SCK10
SCK10
SCL10
SCL10
SCL10
SCL10
SCL10
(input)
(input)
(input)
P04
P04
Pin Function
SI10/SDA10/
P03/RxD1
P03/RxD1
RxD1/P03
SDA10
SDA10
SDA10
SDA10
SDA10
Note 2
SI10
SI10
SI10
SI10
P03
P03
P03
P03
TxD1/P02
SO10/
SO10
SO10
SO10
SO10
TxD1
P02
P02
P02
P02
P02
P02
P02
P02
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