UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 946

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
23.4.1 When used as reset
(1) When detecting level of supply voltage (V
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(a) When LVI default start function stopped is set (LVIOFF = 1)
• When starting operation
• When stopping operation
Be sure to clear (0) the LVIMD bit and then the LVION bit by using a 1-bit memory manipulation instruction.
Cautions 1. Be sure to execute <1>. When LVIMK = 0, an interrupt may occur immediately after the
Figure 23-5 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <7> above.
<1>
<2>
<3>
<4>
<5>
<6>
<7>
Mask the LVI interrupt (LVIMK = 1).
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection
Set bit 7 (LVION) of the LVIM register to 1 (enables LVI operation).
Use software to wait for the following periods of time (Total 210
Wait until it is checked that (supply voltage (V
Set bit 1 (LVIMD) of the LVIM register to 1 (generates reset when the level is detected).
(V
register (LVIS).
register.
• Operation stabilization time (10
• Minimum pulse width (200
DD
2. If supply voltage (V
)) (default value).
processing in <4>.
reset signal is not generated.
DD
μ
) ≥ detection voltage (V
s (MIN.))
DD
μ
)
s (MAX.))
DD
) ≥ detection voltage (V
CHAPTER 23 LOW-VOLTAGE DETECTOR
LVI
) when the LVIMD bit is set to 1, an internal
μ
s).
LVI
)) by bit 0 (LVIF) of the LVIM
946