UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 826

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UPD78F1009GB-GAH-AX

Manufacturer Part Number
UPD78F1009GB-GAH-AX
Description
MCU 16BIT 78K0R/KX3-L 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet

Specifications of UPD78F1009GB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1009GB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(1) Start condition ~ address ~ data
Notes 1. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during master transmission.
(communication status)
(communication status)
(wait cancellation)
(8 or 9 clock wait)
(wait cancellation)
(transmit/receive)
(8 or 9 clock wait)
(transmit/receive)
(ACK detection)
(ACK detection)
(ST detection)
(SP detection)
(ACK control)
(ACK control)
Master side
(ST trigger)
(SP trigger)
SCL0 (bus)
SDA0 (bus)
(clock line)
(data line)
Slave side
(interrupt)
(interrupt)
WREL
INTIICA
Bus line
INTIICA
2. Make sure that the time between the fall of the SDA0 pin signal and the fall of the SCL0 pin signal is at
3. To cancel slave wait, write “FFH” to IICA or set the WREL bit.
MSTS
MSTS
WTIM
WREL
ACKD
ACKE
ACKD
ACKE
WTIM
TRC
SPD
TRC
IICA
STT
SPT
IICA
STD
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4)
least 4.0
: Wait state by slave device
: Wait state by master and slave devices
μ
<1>
H
H
L
L
H
H
L
L
s when specifying standard mode and at least 0.6
Figure 15-32. Example of Master to Slave Communication
Note 2
<2>
AD6
Start condition
AD5
AD4
Slave address
AD3
AD2
CHAPTER 15 SERIAL INTERFACE IICA
AD1
μ
s when specifying fast mode.
AD0
W
<3>
ACK
<5>
<4>
Note 1
<6>
D
1
7
Note 3
826

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