UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 802

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(3) Slave operation
The processing procedure of the slave operation is as follows.
Basically, the slave operation is event-driven. Therefore, processing by the INTIICA interrupt (processing that must
substantially change the operation status such as detection of a stop condition during communication) is
necessary.
In the following explanation, it is assumed that the extension code is not supported for data communication. It is
also assumed that the INTIICA interrupt servicing only performs status transition processing, and that actual data
communication is performed by the main processing.
Therefore, data communication processing is performed by preparing the following three flags and passing them to
the main processing instead of INTIICA.
<1> Communication mode flag
<2> Ready flag
<3> Communication direction flag
This flag indicates the following two communication statuses.
• Clear mode:
• Communication mode: Status in which data communication is performed (from valid address detection to
This flag indicates that data communication is enabled. Its function is the same as the INTIICA interrupt for
ordinary data communication. This flag is set by interrupt servicing and cleared by the main processing.
Clear this flag by interrupt servicing when communication is started. However, the ready flag is not set by
interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted without the flag
being cleared (an address match is interpreted as a request for the next data).
This flag indicates the direction of communication. Its value is the same as the TRC bit.
IICA
Status in which data communication is not performed
stop condition detection, no detection of ACK from master, address mismatch)
INTIICA
Setting
Interrupt servicing
Setting
Data
CHAPTER 15 SERIAL INTERFACE IICA
Flag
Main processing
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