UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 46

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Clock output/buzzer output
10-bit resolution A/D converter
(AV
Comparators
Programmable gain amplifiers
Serial interface
Multiplier/divider
DMA controller
Vectored interrupt
sources
Key interrupt
Reset
Power-on-clear circuit
Low-voltage detector
On-chip debug function
Power supply voltage
Operating ambient temperature
Notes 1. The
REF
= 1.8 to 5.5 V)
2. The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
Item
μ
Internal
External
I
2
C bus
PD78F1029 and
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
• CSI: 2 channels/UART: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I
• CSI: 1 channel/UART: 1 channel/simplified I
• UART supporting LIN-bus: 1 channel
• CSI: 2 channels/UART: 1 channel (
• 16 bits × 16 bits = 32 bits (multiplication)
• 32 bits ÷ 32 bits = 32 bits (division)
2 channels
8 channels (KR0 to KR7)
• Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-clear
• Internal reset by low-voltage detector
• Internal reset by illegal instruction execution
• Internal reset by a reset processing check error
• Power-on-reset:
• Power-down-reset: 1.59 ±0.09 V
1.91 V to 4.22 V (16 stages)
Provided
V
T
A
DD
μ
(peripheral hardware clock: f
(Subsystem clock: f
= −40 to +85 °C
PD78F1030 don’t have the FBGA package.
= 1.8 to 5.5 V
33
78K0R/KF3-L
12 channels
1.61 ±0.09 V
SUB
= 32.768 kHz operation)
MAIN
= 20 MHz operation)
μ
PD78F1027, 78F1028, 78F1029, 78F1030)
35
1 channel
2
2
Note 2
C: 1 channel
C: 1 channel
13
2
−
−
33
CHAPTER 1 OUTLINE
78K0R/KG3-L
16 channels
35
(2/2)
46