UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 897

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
18.5 Interrupt Servicing Operations
18.5.1 Maskable interrupt request acknowledgment
flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are
in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged
during servicing of a higher priority interrupt request.
Table 18-6 below.
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same priority
level, the request with the highest default priority is acknowledged first.
the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are
transferred to the ISP1 and ISP0 flags. The vector table data determined for each interrupt request is the loaded into the
PC and branched.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK)
The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed in
For the interrupt request acknowledgment timing, see Figures 18-13 and 18-14.
Note If an interrupt request is generated just before the RET instruction, the wait time becomes longer.
Remark 1 clock: 1/f
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 18-12 shows the interrupt request acknowledgment algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC,
Restoring from an interrupt is possible by using the RETI instruction.
Table 18-6. Time from Generation of Maskable Interrupt Until Servicing
CLK
Servicing time
(f
CLK
: CPU clock)
9 clocks
Minimum Time
CHAPTER 18 INTERRUPT FUNCTIONS
14 clocks
Maximum Time
Note
897