UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 625

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
14.4.2 Stopping the operation by channels
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The stopping of the operation by channels is set using each of the following registers.
SOE0
SOE1
SOE2
SEm
STm
(a) Serial channel stop register m (STm) … This register is a trigger register that is used to enable
(b) Serial Channel Enable Status Register m (SEm) … This register indicates whether data
Note
(Remark is listed on the next page.)
(c) Serial output enable register m (SOEm) … This register is a register that is used to enable or stop
stopping communication/count by each channel.
transmission/reception operation of each channel is enabled or stopped.
output of the serial communication operation of each channel.
*
*
*
*
*
With a channel whose operation is stopped, the value of the CKOmn bit of the SOm register can be set by
software.
Because the STmn bit is a trigger bit, it is cleared immediately when Semn = 0.
For channel n, whose serial output is stopped, the SO10 and SO12 bits value of the SO1 register can be set by software.
For channel n, whose serial output is stopped, the SO20, SO21 bits value of the SO2 register can be set by software.
The SEm register is a read-only status register, whose operation is stopped by using the STm register.
For channel n, whose serial output is stopped, the SO0n bit value of the SO0 register can be set by software.
Figure 14-27. Each Register Setting When Stopping the Operation by Channels (1/2)
15
15
15
15
15
0
0
0
0
0
Those bits are invalid while operating serial allay unit 2.
14
14
14
14
14
0
0
0
0
0
1: Clears the SEmn bit to 0 and stops the communication operation
13
13
13
13
13
0
0
0
0
0
12
12
12
12
12
0
0
0
0
0
11
11
11
11
11
0
0
0
0
0
10
10
10
10
10
0
0
0
0
0
0: Stops output by serial communication operation
0: Stops output by serial communication operation
0: Stops output by serial communication operation
0
9
0
9
0
0
0
9
9
9
0
8
0
8
0
0
0
8
8
8
0
7
0
7
7
0
7
0
7
0
0: Operation stops
0
6
0
6
6
0
6
0
6
0
0
5
0
5
0
0
0
5
5
5
CHAPTER 14 SERIAL ARRAY UNIT
4
0
4
0
0
0
0
4
4
4
SEm3
STm3
0/1
0/1
Note
Note
3
3
3
0
3
0
3
0
SOE02
SOE12
SEm2
STm2
0/1
0/1
0/1
0/1
Note
Note
2
2
2
2
2
0
SOE01
SOE21
STm1
SEm1
0/1
0/1
0/1
0/1
1
1
1
1
0
1
SOE00
SOE10
SOE20
STm0
SEm0
0/1
0/1
0/1
0/1
0/1
0
0
0
0
0
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