UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 889

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is
entered.
The IF0L, IF0H, IF1L, IF1H, IF2L, and IF2H registers can be set by a 1-bit or 8-bit memory manipulation instruction.
When the IF0L and IF0H registers, the IF1L and IF1H registers, and the IF2L and IF2H registers are combined to
form 16-bit registers IF0, IF1, and IF2, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
Address: FFFE0H After reset: 00H R/W
Address: FFFE1H
Address: FFFE2H
Address: FFFE3H
Address: FFFD0H
Symbol
Symbol
Symbol
Symbol
Symbol
Figure 18-7. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (1/2)
IF0H
IF1H
IF0L
IF1L
IF2L
increases by 2 clocks.
SREIF0
TMIF03
TMIF04
PIF10
PIF5
<7>
<7>
<7>
<7>
<7>
After reset: 00H
After reset: 00H
After reset: 00H
After reset: 00H
CSIIF01
TMIF02
TMIF13
SRIF0
PIF4
PIF9
<6>
<6>
<6>
<6>
<6>
R/W
R/W
R/W
R/W
CSIIF00
TMIF01
STIF0
PIF3
PIF6
PIF8
<5>
<5>
<5>
<5>
<5>
DMAIF1
CSIIF20
TMIF00
IICIF20
STIF2
PIF2
PIF7
<4>
<4>
<4>
<4>
<4>
DMAIF0
IICAIF
SRIF2
KRIF
PIF1
<3>
<3>
<3>
<3>
<3>
CHAPTER 18 INTERRUPT FUNCTIONS
SREIF3
SREIF1
TMIF07
RTCIIF
PIF0
<2>
<2>
<2>
<2>
<2>
TMIF06
RTCIF
SRIF3
SRIF1
LVIIF
<1>
<1>
<1>
<1>
<1>
CSIIF10
WDTIIF
TMIF05
IICIF10
STIF3
STIF1
ADIF
<0>
<0>
<0>
<0>
<0>
889