UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 918

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
Notes 1. Those are not mounted onto 40-pin product of the 78K0R/KC3-L.
Remark f
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Item
System clock
CPU
Flash memory
RAM
Port (latch)
Timer array unit
Real-time counter (RTC)
Watchdog timer
Clock output/buzzer output
A/D converter
Programmable gain amplifier
Comparator
Serial array unit (SAU)
Serial interface (IICA)
Multiplier/divider
DMA controller
Power-on-clear function
Low-voltage detection function
External interrupt
Key interrupt function
Main system clock
Subsystem
clock
f
IL
2. Those are not mounted onto 40-pin and 44-pin products of the 78K0R/KC3-L.
3. 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L only.
Note 1
f
f
f
f
IH
X
EX
XT
IL
STOP Mode Setting
Note 3
:
:
:
: External main system clock
: XT1 clock
Internal high-speed oscillation clock
X1 clock
Internal low-speed oscillation clock
Note 2
Note 1
f
f
f
f
IH
X
EX
XT
Note 2
Note 3
Clock supply to the CPU is stopped
Stopped
Status before STOP mode was set is retained
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H)
• WDTON = 0: Stops
• WDTON = 1 and WDSTBYON = 1: Oscillates
• WDTON = 1 and WDSTBYON = 0: Stops
Operation stopped
Operation stopped
The value is retained
Status before STOP mode was set is retained
Operation disabled
Operable
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H)
• WDTON = 0: Stops
• WDTON = 1 and WDSTBYON = 1: Operates
• WDTON = 1 and WDSTBYON = 0: Stops
Operable only when subsystem clock is selected as the count clock
Operation disabled
Wakeup by address match operable
Operation disabled
Operable
When CPU Is Operating on
Oscillation Clock (f
Internal High-Speed
Table 20-2. Operating Statuses in STOP Mode
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock
IH
)
When CPU Is Operating on
X1 Clock (f
X
CHAPTER 20 STANDBY FUNCTION
)
External Main System Clock
When CPU Is Operating on
(f
EX
)
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