UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 801

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UPD78F1009GB-GAH-AX

Manufacturer Part Number
UPD78F1009GB-GAH-AX
Description
MCU 16BIT 78K0R/KX3-L 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet

Specifications of UPD78F1009GB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1009GB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission and
2. To use the device as a master in a multi-master system, read the MSTS bit each time interrupt INTIICA
3. To use the device as a slave in a multi-master system, check the status by using the IICA status register
reception formats.
has occurred to check the arbitration result.
(IICS) and IICA flag register (IICF) each time interrupt INTIICA has occurred, and determine the
processing to be performed next.
No
No
EXC = 1 or COI = 1?
interrupt occurs?
interrupt occurs?
Slave operation
Transfer end?
Writing IICA
Writing IICA
MSTS = 1?
ACKD = 1?
MSTS = 1?
ACKD = 1?
TRC = 1?
WTIM = 1
Restart?
INTIICA
INTIICA
STT = 1
Figure 15-29. Master Operation in Multi-Master System (3/3)
C
C
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Starts communication
(specifies an address and transfer direction).
Starts transmission.
Waits for detection of ACK.
Waits for data transmission.
Does not participate
in communication.
SPT = 1
END
2
2
1
CHAPTER 15 SERIAL INTERFACE IICA
WTIM = WREL = 1
interrupt occurs?
interrupt occurs?
Transfer end?
Reading IICA
MSTS = 1?
MSTS = 1?
WREL = 1
ACKE = 1
WTIM = 0
ACKE = 0
INTIICA
INTIICA
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Starts reception.
Waits for data reception.
Waits for detection of ACK.
2
2
801

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