UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 349

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(4) Oscillation stabilization time counter status register (OSTC)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case,
The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset signal is generated, the STOP instruction and MSTOP (bit 7 of clock operation status control register
(CSC)) = 1 clear the OSTC register to 00H.
Remark The oscillation stabilization time counter starts counting in the following cases.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or subsystem clock is being used
• If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as
as the CPU clock.
the CPU clock with the X1 clock oscillating.
Note The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
X1 clock
External main system
clock
Subsystem clock
Internal high-speed
oscillation clock
• When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 → MSTOP = 0)
• When the STOP mode is released
Clock
Table 7-3. Condition Before Stopping Clock Oscillation and Flag Setting
Note
CPU and peripheral hardware clocks operate with a clock
other than the high-speed system clock.
(CLS = 0 and MCS = 0, or CLS = 1)
CPU and peripheral hardware clocks operate with a clock
other than the subsystem clock.
(CLS = 0)
CPU and peripheral hardware clocks operate with a clock
other than the internal high-speed oscillator clock and 20
MHz internal high-speed oscillation clock.
(CLS = 0 and MCS = 1, or CLS = 1)
(Invalidating External Clock Input)
Condition Before Stopping Clock
CHAPTER 7 CLOCK GENERATOR
MSTOP = 1
XTSTOP = 1
HIOSTOP = 1
Setting of CSC
Register Flags
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