UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 464

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
8.7.5 Operation as input signal high-/low-level width measurement
width (high-level width/low-level width) of TImn can be measured. The signal width of TImn can be calculated by the
following expression.
and the TImn pin start edge detection wait status is set.
detected, the counter counts up from 0000H in synchronization with the count clock. When the valid capture edge (falling
edge of the TImn pin input when the high-level width is to be measured) is detected later, the count value is transferred to
timer data register mn (TDRmn) and, at the same time, INTTMmn is output. If the counter overflows at this time, the OVF
bit of timer status register mn (TSRmn) is set to 1. If the counter does not overflow, the OVF bit is cleared. The TCRmn
register stops at the value “value transferred to the TDRmn register + 1”, and the TImn pin start edge detection wait status
is set. After that, the above operation is repeated.
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
and CISmn0 bits of the TMRmn register.
the TEmn bit is 1.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
By starting counting at one edge of the TImn pin input and capturing the number of counts at another edge, the signal
Timer/counter register mn (TCRmn) operates as an up counter in the capture & one-count mode.
When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TEmn bit is set to 1
When the TImn pin input start edge (rising edge of the TImn pin input when the high-level width is to be measured) is
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
Whether the high-level width or low-level width of the TImn pin is to be measured can be selected by using the CISmn1
Because this function is used to measure the signal width of the TImn pin input, the TSmn bit cannot be set to 1 while
CISmn1, CISmn0 of TMRmn register = 10B: Low-level width is measured.
CISmn1, CISmn0 of TMRmn register = 11B: High-level width is measured.
Signal width of TImn input = Period of count clock × ((10000H × TSRmn: OVF) + (Capture value of TDRmn + 1))
Caution When using a channel to implement the LIN-bus, set bit 1 (ISC1) of the input switch control
Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer
register (ISC) to 1. In the following descriptions, read TImn as RxD0 if using the 78K0R/KC3-L,
78K0R/KD3-L, or 78K0R/KE3-L, and as RxD3 if using the 78K0R/KF3-L or 78K0R/KG3-L.
mode register mn (TMRmn), so an error equivalent to one operation clock occurs.
CHAPTER 8 TIMER ARRAY UNIT
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