UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 410

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07)
(4) Timer status register mn (TSRmn)
TSRmn
Symbol
The TSRmn register indicates the overflow status of the counter of channel n.
The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode
(MDmn3 to MDmn1 = 110B). It will not be set in any other mode. See Table 8-3 for the operation of the OVF bit in
each operation mode and set/clear conditions.
The TSRmn register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the TSRmn register can be set with an 8-bit memory manipulation instruction with TSRmnL.
Reset signal generation clears this register to 0000H.
Remark
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
F01D0H, F01D1H (TSR10) to F01D6H, F01D7H (TSR13)
When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow.
• Capture mode
• Capture & one-count mode
• Interval timer mode
• Event counter mode
• One-count mode
OVF
15
0
1
0
The OVF bit does not change immediately after the counter has overflowed, but changes upon the
subsequent capture.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
Table 8-3. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode
Timer operation mode
Overflow does not occur.
Overflow occurs.
14
0
13
0
Figure 8-12. Format of Timer Status Register mn (TSRmn)
12
0
11
0
clear
set
clear
set
OVF bit
10
0
Counter overflow status of channel n
9
0
When no overflow has occurred upon capturing
When an overflow has occurred upon capturing
8
0
mn = 00 to 07, 10 to 13
After reset: 0000H
(Use prohibited, not set and not cleared)
7
0
6
0
Set/clear conditions
CHAPTER 8 TIMER ARRAY UNIT
5
0
R
−
4
0
3
0
2
0
1
0
OVF
0
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