UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 445

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
8.7 Independent Channel Operation Function of Timer Array Unit
8.7.1 Operation as interval timer/square wave output
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(1) Interval timer
(2) Operation as square wave output
The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals.
The interrupt generation period can be calculated by the following expression.
In products other than the 78K0R/KC3-L (40-pin), A subsystem clock divided by four (f
count clock, in addition to CKm0 and CKm1. Consequently, the interval timer can be operated with the count clock
fixed to f
the clock selected as f
of timer array unit (timer channel stop register m (TTm) = 00FFH).
TOmn performs a toggle operation as soon as INTTMmn has been generated, and outputs a square wave with a
duty factor of 50%.
The period and frequency for outputting a square wave from TOmn can be calculated by the following expressions.
Timer/counter register mn (TCRmn) operates as a down counter in the interval timer mode.
The TCRmn register loads the value of timer data register mn (TDRmn) at the first count clock after the channel
start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1. If the MDmn0 bit of timer mode register
mn (TMRmn) is 0 at this time, INTTMmn is not output and TOmn is not toggled. If the MDmn0 bit of the TMRmn
register is 1, INTTMmn is output and TOmn is toggled.
After that, the TCRmn register count down in synchronization with the count clock.
When TCRmn = 0000H, INTTMmn is output and TOmn is toggled at the next count clock. At the same time, the
TCRmn register loads the value of the TDRmn register again. After that, the same operation is repeated.
The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid from the
next period.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
Generation period of INTTMmn (timer interrupt) = Period of count clock × (Set value of TDRmn + 1)
• Period of square wave output from TOmn = Period of count clock × (Set value of TDRmn + 1) × 2
• Frequency of square wave output from TOmn = Frequency of count clock/{(Set value of TDRmn + 1) × 2}
SUB
2.
/4, regardless of the f
f
f
However, in case of the operation of square wave output and the timer output pin (TOmn), mn
changes as below.
78K0R/KC3-L (40-pin):
78K0R/KC3-L (44-pin, 48-pin): mn = 00 to 07
78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
CLK
SUB
: CPU/peripheral hardware clock frequency
: Subsystem clock oscillation frequency
CLK
(change the value of the system clock control register (CKC)) after stopping all channels
CLK
frequency (main system clock, subsystem clock). However, be sure to change
mn = 02 to 07
mn = 00 to 07
mn = 00 to 07, 10 to 13
CHAPTER 8 TIMER ARRAY UNIT
SUB
/4) can be selected as the
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