UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 393

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
8.2 Configuration of Timer Array Unit
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Timer array unit includes the following hardware.
Notes 1. 40-pin product of the 78K0R/KC3-L does not have a SLTI and SLTO pins.
Remark
Timer/counter
Register
Timer input
Timer output
Control registers
2. Set the PER2 register in the 78K0R/KC3-L, 78K0R/KD3-L, and 78K0R/KE3-L. Set the PER0 register in the
3. The port mode registers (PMxx) and port registers (Pxx) to be set differ depending on the product. for
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00 to 07
78K0R/KF3-L, 78K0R/KG3-L:
78K0R/KF3-L and 78K0R/KG3-L.
details, see 8. 3 (15) Port mode registers 0, 1, 3 to 6, 13, 14 (PM0, PM1, PM3 to PM6, PM13, PM14).
Item
TI00 to TI07 (78K0R/KC3-L (40-pin) : TI02 to
TI07), SLTI
TO00 to TO07(78K0R/KC3-L (40-pin) : TO02
to TO07), SLTO
<Registers of unit setting block>
• Peripheral enable registers 0, 2 (PER0, PER2)
• Timer clock select register m (TPSm)
• Timer channel enable status register m (TEm)
• Timer channel start register m (TSm)
• Timer channel stop register m (TTm)
• Timer input select register m (TISm)
• Timer output enable register m (TOEm)
• Timer output register m (TOm)
• Timer output level register m (TOLm)
• Timer output mode register m (TOMm)
<Registers of each channel>
• Timer mode register mn (TMRmn)
• Timer status register mn (TSRmn)
• Input switch control register (ISC)
• Noise filter enable registers 1, 2 (NFEN1, NFEN2)
• Port mode register (PMxx)
• Port register (Pxx)
Timer/counter register mn (TCRmn)
Timer data register mn (TDRmn)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L
Table 8-1. Configuration of Timer Array Unit
Note 1
pins, RxD0 pin (for LIN-bus)
Note 1
Note 3
pins, output controller
Note 3
mn = 00 to 07, 10 to 13
Configuration
TI00 to TI07, TI10 to TI13, RxD3 pin (for LIN-
bus)
TO00 to TO07, TO10 to TO13, output
controller
Note 2
CHAPTER 8 TIMER ARRAY UNIT
78K0R/KF3-L, 78K0R/KG3-L
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