UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 678

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(2) Operation procedure
Cautions 1. After setting the SAUmEN bit of peripheral enable register 0/1 (PER0/PER1) to 1, be sure to
2. Be sure to set transmit data to the SlOp register before the clock from the master is started.
set serial clock select register m (SPSm) after 4 or more f
Figure 14-67. Initial Setting Procedure for Slave Transmission/Reception
Setting the PER0/PER1 register
Changing setting of the SOEm register
Setting the SMRmn register
Setting the SCRmn register
Setting the SDRmn register
Writing to the SSm register
Setting the SPSm register
Setting the SOm register
Starting communication
Starting initial setting
Setting port
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set bits 15 to 9 to 0000000B for baud
rate setting.
Set the initial output level of the serial
data (SOmn).
Set the SOEmn bit to 1 and enable data
output of the target channel.
Enable data output of the target channel
by setting a port register and a port
mode register.
Set the SSmn bit of the target channel to 1
and set the SEmn bit to 1 (to enable
Set transmit data to the SIOp register
(bits 7 to 0 of the SDRmn register) and
wait for a clock from the master.
CHAPTER 14 SERIAL ARRAY UNIT
CLK
clocks have elapsed.
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