UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 450

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
TAU
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
(Note and Remark are listed on the next page.)
Sets the TAU0EN and TAU1EN bits of peripheral enable
registers 0, 2 (PER0, PER2) to 1.
Sets timer clock select register m (TPSm).
Sets timer mode register mn (TMRmn) (determines
operation mode of channel).
Sets the TISmn bit to 1 (f
the count clock.
Sets interval (period) value to timer data register mn
(TDRmn).
To use the TOmn output
Sets the TOEmn bit to 1 and enables operation of TOmn.
(Sets the TOEmn bit to 1 only if using TOmn output and
Sets the TSmn bit to 1.
Set values of the TMRmn register, TOMmn, and TOLmn
bits cannot be changed.
Set value of the TDRmn register can be changed.
The TCRmn register can always be read.
The TSRmn register is not used.
Set values of the TOm and TOEm registers can be
changed.
The TTmn bit is set to 1.
The TOEmn bit is cleared to 0 and value is set to the TOmn bit.
resuming operation.).
Determines clock frequencies of CKm0 and CKm1.
Clears the TOMmn bit of timer output mode register m
(TOMm) to 0 (master channel output mode).
Clears the TOLmn bit to 0.
Sets the TOmn bit and determines default level of the
TOmn output.
Clears the port register and port mode register to 0.
The TSmn bit automatically returns to 0 because it is a
trigger bit.
The TTmn bit automatically returns to 0 because it is a
trigger bit.
Figure 8-44. Operation Procedure of Interval Timer/Square Wave Output Function (1/2)
Software Operation
SUB
/4) when f
Note
SUB
/4 is selected as
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOmn pin goes into Hi-Z output state.
The TOmn default setting level is output when the port mode
register is in the output mode and the port register is 0.
TOmn does not change because channel stops operating.
The TOmn pin outputs the TOmn set level.
TEmn = 1, and count operation starts.
Counter (TCRmn) counts down. When count value reaches
0000H, the value of the TDRmn register is loaded to the
TCRmn register again and the count operation is continued.
By detecting TCRmn = 0000H, INTTMmn is generated and
TOmn performs toggle operation.
After that, the above operation is repeated.
TEmn = 0, and count operation stops.
The TOmn pin outputs the TOmn bit set level.
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
Value of the TDRmn register is loaded to timer/counter
register mn (TCRmn) at the count clock input. INTTMmn is
generated and TOmn performs toggle operation if the
MDmn0 bit of the TMRmn register is 1.
The TCRmn register holds count value and stops.
The TOmn output is not initialized but holds current status.
CHAPTER 8 TIMER ARRAY UNIT
Hardware Status
450